1. FIELD OF THE INVENTION
This invention relates to improvements in circuitry for buffering electronic circuits to each other, and more particularly to improvements in circuitry for buffering a circuit that has an output voltage at a high output impedance to a low input impedance load or load circuit while maintaining an accurate output voltage, regardless of the load conditions.
2. DESCRIPTION OF THE PRIOR ART
It is a common technique to interpose a "buffer" amplifier, usually incorporating an emitter-follower circuit, between two circuits to minimize the interaction between the two circuits and to isolate the first circuit from the second. Typically the buffer will have a high input impedance to impose only light loading on the first circuit, and a low output impedance to enable the buffer to drive heavy loads, such as those presenting small load resistances. Without a buffer amplifier between a circuit having a high output impedance and a circuit with a low input impedance, most of the signal is dropped across the internal impedance of the source. Properly set up, the buffer amplifier will present an output voltage equal to its input voltage.
There are typically two ways to implement the buffer amplifier. The first way is using open loop circuits in which there is no voltage feedback. The second way is using closed loop circuits in which there is voltage feedback. One of the advantages of open loop circuits is that they offer greater response speed than closed loop circuits, generally having shorter propagation delay. The problem with open loop circuits is that they are imprecise, since there is no way of correcting output signal errors. On the other hand, one of the advantages of closed loop circuits is the greater accuracy and precision that feedback makes possible. The drawbacks of closed loop circuits are that gain is traded off for precision, and the response speed is slower, since the propagation delay is increased. Also, the stability of the loop in closed loop circuits becomes a problem, since out-of-control oscillations may occur; therefore, the bandwidth of the loop is usually reduced to insure stability. Thus, if there is a requirement for wide bandwidth, the use of a voltage feedback loop may be inappropriate and an open loop approach may be necessary.
When constructing buffer amplifier circuits that use several cascaded bipolar transistor stages, it is necessary to provide a "matching" of the base to emitter voltages (V.sub.BE 's) of the transistors in the various stages to enable the output voltage to be a replica, as precisely as possible, of the input voltage. Such matching can be achieved by proper control of the relevant parameters, such as the collector currents, the type of transistors (i.e., NPN or PNP), the areas or sizes of the emitters, the geometry of the devices, and the collector-emitter voltages. In a bipolar transistor V.sub.BE follows the formula: ##EQU1## where V.sub.T is approximately equal to 26 mV and I.sub.a is a technology-dependent parameter which is proportional to the emitter area of the transistor. Therefore, V.sub.BE decreases by approximately 18 mV for every doubling of the emitter area. Not only is the V.sub.BE directly affected by the area of the emitter of a transistor, but also by collector current. Therefore, V.sub.BE 's can be closely matched in the stages by appropriately sizing the emitters and the relative collector currents.
Thus, the usual method of matching V.sub.BE 's involves imposing equal currents through transistors that are of the same type (i.e., both NPNs or PNPs) and emitter size. For example, two NPN transistors of equal size handling the same collector current will have equal V.sub.BE 's. However, an NPN transistor and a PNP transistor will generally have different V.sub.BE 's for the same collector current. In the past, at times the V.sub.BE 's of NPNs have been matched to PNPs, but only for establishing desired static conditions, such as biasing. V.sub.BE matching has not been used for transistors carrying dynamic signals. In light of the formula given above, however, it becomes apparent that an approximation of the voltage drop (V.sub.BE) on an NPN transistor to that of a PNP transistor for the same current may be obtained by appropriately scaling their relative emitter areas (if the two devices are not intrinsically similar due to their construction).
It can be seen that the simplest multiple transistor buffer amplifier comprises two cascaded "emitter follower" stages that are of opposite polarity, i.e., one NPN and one PNP, to partially compensate for the V.sub.BE voltage drops.
Not only is the V.sub.BE of a transistor in one stage typically different from the V.sub.BE of a transistor in another stage, unless they are purposely made equal by imposing special conditions, but the transistors will also tend to have different collector currents according to the respective loads. Accordingly, what is needed is a circuit that matches the V.sub.BE of an NPN transistor in one stage to the V.sub.BE of a PNP transistor in another stage independent of the current in the load to achieve at least a first order load independence. For transistors which have V.sub.BE 's within a certain range, the circuit should automatically establish the required collector currents in the two stages so that equal V.sub.BE 's are continuously maintained. This current will be dependent on the transistor type and will not necessarily be equal in both stages.